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TDA7401
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER
FOUR HIGH PASS CHANNELS ONE STEREO LOW PASS CHANNEL WITH GAIN CONTROL DIRECT MUTE PIN FULLY PROGRAMMABLE VIA I2C BUS DESCRIPTION The TDA7401 is an upgrade of the TDA7435 audioprocessor. Due to a highly linear signal processing, using CMOS-switching techniques very low distortion and very low noise are obtained. Second order high pass and low pass filters with programmable corner frequencies provide the loudspeaker equalization. BLOCK DIAGRAM
SO28 ORDERING NUMBER: TDA7401D
Very low DC stepping is obtained by using a BICMOS technology.
MUTE 22 21 20 19 18 17 16 15 HP FILTER HP FILTER HP FILTER MUTE HP FILTER 3
SDA SCL DGND AGND CREF 27 26 25 24 23
VCC 28 12
HP FL 1 HP FL 2 HP FR 1 HP FR 2 HP RL 1 HP RL 2 HP RR 1 HP RR 2
I2C BUS
SUPPLY
OUT REF
10 11 13 14 9 MUX 8
HP FL OUT HP FR OUT HP RL OUT HP RR OUT AUX 2 OUT L AUX 2 OUT R
AUX 1 IN L AUX 1 IN R
1 2 GAIN +20/-79dB 4 5 7 CR2 6 CL2
D98AU822A
CR1 CL1
January 1999
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TDA7401
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Parameter Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Value 10.5 -40 to 85 -55 to 150 Unit V C C
PIN CONNECTION
AUX 1 IN L AUX 1 IN R MUTE CR1 CL1 CL2 CR2 AUX 2 OUT R AUX 2 OUT L HP FL OUT HP FR OUT OUT REF HP RL OUT HP RR OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D98AU823A
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC SDA SCL DGND AGND CREF HP FL 1 HP FL 2 HP FR 1 HP FR 2 HP RL 1 HP RL 2 HP RR 1 HP RR 2
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-pins Value 65 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC VREF Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Reference Voltage Output (pin 12) -80 4.2 Parameter Min. 6 2.1 Typ. 9 2.6 0.01 106 100 4.5 Max. 10.2 0.08 Unit V Vrms % dB dB V
4.8
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TDA7401
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol RI VCL SI G MAX AMAX ASTEP EA ET VDC Parameter Input Resistance Clipping Level Input Separation Maximum Input Gain Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps Test Condition Min. 37.5 2.1 80 Typ. 50 2.6 100 20 79 1 0 Max. 62.5 Unit K VRMS dB dB dB dB dB dB dB mV mV Vrms K V K M Vrms dB 2.2 62.5 V K
INPUT STAGE: AUX1
d 0.3%
GAIN CONTROL
G = -20 to +20dB G = -60 to -20dB Adiacent Attenuation Steps From 0dB to GMIN d = 0.3% AC coupled
0.5 -1.25 -4
0.1 0.5 2.1 2 4.2 2.6 30 4.5 170 2.6 100 1.7 50
1.5 +1.25 3 2 3 5
AUDIO OUTPUT (Pin 8 - 9, 10 - 14)
Vclip RL RO VDC R1 R2 VCL Clipping Level Output Load Resistance Output Impedance DC Voltage Level Resistance at pin HP1 Resistance at pin HP2 Clipping Level Mute Attenuation Mute Threshold Pullup Resistor (pin 3) (note 1)
100 4.8 212.5
STAGE: HP FILTER
HIGHPASS BYTE = XXXX1000 d 0.3% 127.5 1 2.1 80 1.2 37.5
MUTE
AMUTE VTHM RINT
GENERAL
VCC ICC PSRR eNO Supply Voltage Supply Current Power Supply Rejection Ratio Output Noise f = 1KHz Non Inverting Output Muted (B = 20 to 20kHz flat) All Gains 0dB (B = 20 to 20kHz flat) All Gains = 0dB; VO = 1Vrms VIN =1V 6 7 60 9 8 70 3.5 5 106 100 0.01 10.2 9 15 15 V mA dB V V dB dB % V V 5 0.4 A V
S/N SC d VIL VlH IlN VO
Signal to Noise Ratio Channel Separation Distortion Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge
80
0.08 0.8
BUS INPUTS
2.5 VIN = 0.4V IO = 1.6mA -5 0.1
Note 1: Internal pullup resistor to 3.3V; "LOW" = mute active
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TDA7401
Figure 1. HP Filter
56.5K
18.7K
9.4K
7.7K
56K
4.4K
3.6K
12.5K
100nF
HP2
100nF + HP1 6.2K 3.5K 2.1K 3.8K 4.7K 9.4K 28K -
28K
R1 = EQUIVALENT RESISTANCE AT PIN HP1 R2 = EQUIVALENT RESISTANCE AT PIN HP2
D98AU836
Figure 2. Application Circuit
P
10F
DGND
AGND
CREF
VCC VCC 28 12 OUT REF 100nF 10F
MUTE 100nF 100nF HP FL IN 100nF 100nF HP FR IN 100nF 100nF HP RL IN HP FL 1 HP FL 2 HP FR 1 HP FR 2 HP RL 1 HP RL 2 100nF 100nF HP RR 1 HP RR 2 22 21 20 19 18 17 16 15 HP FILTER HP FILTER HP FILTER MUTE HP FILTER 3
SDA 27
SCL
26
25
24
23
I2C BUS
SUPPLY
OUT REF
10 11 13 14 9 MUX 8
HP FL OUT HP FR OUT HP RL OUT HP RR OUT AUX L OUT AUX R OUT
HP FL OUT HP FR OUT HP RL OUT HP RR OUT AUX L OUT AUX R OUT
HP RR IN
220nF AUX L IN AUX R IN 220nF
AUX 1 IN L AUX 1 IN R
1 2 GAIN +20/-79dB 4 CR1 100nF 5 CL1 7 CR2 6 CL2 100nF
D98AU835
100 100 nF nF
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TDA7401
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7401 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 2, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must conFigure 3. Data Validity on the I2CBUS tain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 4). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 4. Timing Diagram of I2CBUS
Figure 5. Acknowledge on the I2CBUS
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TDA7401
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines
read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB S 1 0 0 0 1 0
LSB
MSB X X I
LSB X A2 A1 A0 ACK
MSB DATA
LSB
AC P K
1 R/W ACK X
ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used AUTO INCREMENT If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled SUBADDRESS (receive mode)
MSB X X X I X D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 Not used Mode Gain AUX 1 L Gain AUX 1 R High Pass Filter FL High Pass Filter FR High Pass Filter RL High Pass Filter RR FUNCTION
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TDA7401
MODE
MSB D7 D6 D5 D4 D3 D2 D1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 LSB D0 X High Pass Mute ON High Pass Mute OFF AUX1 Input Mute ON AUX1 Input Mute OFF AUX2 Inverted Output AUX2 Non Inv. Output AUX 2 Output Selection High Pass Filter Front High Pass Filter Rear Aux 1 Input Mute AUX1 Low Pass Filter (C1 = C2 = 100nF) 0 0 1 1 0 1 0 1 Flat 120Hz 80Hz 50Hz FUNCTION
GAIN AUX1L, AUX1R
MSB D7 1 : 1 1 1 : 1 1 0 0 : 0 0 : 0 0 X D6 0 : 0 0 0 : 0 0 0 0 : 0 0 : 1 1 1 D5 0 : 0 0 0 : 0 0 0 0 : 0 0 : 0 0 1 D4 1 : 1 1 0 : 0 0 0 0 : 0 1 : 0 0 X D3 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 X D2 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 X D1 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 X LSB D0 1 : 1 0 1 : 1 0 0 1 : 1 0 : 0 1 X +31dB : +17dB +16dB +15dB : +1dB 0dB 0dB -1dB : -15dB -16dB : -78dB -79dB Mute GAIN AUX1L, R
Note: Is is not recommended to use a gain more than 20dB for system performance reason. In general, the max. gain should be limited by software to the maximum value, which is needed for the system.
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TDA7401
HIGH PASS FILTERS
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 FL, FR, RL, RR
2nd order HP Filter Mode (C1 = C2 = 100nF)
X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fc = 40Hz fc = 60Hz fc = 80Hz fc = 100Hz fc = 120Hz fc = 150Hz fc = 180Hz fc = 220Hz
First order HP Flat Mode
1 0 0 0 fc = 9Hz
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TDA7401
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
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TDA7401
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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